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<p>Video Processing Subsystem configuration structure.  
 <a href="struct_x_v___hdmi_tx_ss1___config.html#details">More...</a></p>
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Data Fields</h2></td></tr>
<tr class="memitem:acfe7283fe422114877f8a4df825c0889"><td class="memItemLeft" align="right" valign="top">u16&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_tx_ss1___config.html#acfe7283fe422114877f8a4df825c0889">DeviceId</a></td></tr>
<tr class="memdesc:acfe7283fe422114877f8a4df825c0889"><td class="mdescLeft">&#160;</td><td class="mdescRight">DeviceId is the unique ID of the device.  <a href="#acfe7283fe422114877f8a4df825c0889">More...</a><br/></td></tr>
<tr class="separator:acfe7283fe422114877f8a4df825c0889"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2fad82bc5ec410236e8995be3b421baf"><td class="memItemLeft" align="right" valign="top">UINTPTR&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_tx_ss1___config.html#a2fad82bc5ec410236e8995be3b421baf">BaseAddress</a></td></tr>
<tr class="memdesc:a2fad82bc5ec410236e8995be3b421baf"><td class="mdescLeft">&#160;</td><td class="mdescRight">BaseAddress is the physical base address of the subsystem address range.  <a href="#a2fad82bc5ec410236e8995be3b421baf">More...</a><br/></td></tr>
<tr class="separator:a2fad82bc5ec410236e8995be3b421baf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a185924b641edacf1f3b4ec5abda27345"><td class="memItemLeft" align="right" valign="top">UINTPTR&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_tx_ss1___config.html#a185924b641edacf1f3b4ec5abda27345">HighAddress</a></td></tr>
<tr class="memdesc:a185924b641edacf1f3b4ec5abda27345"><td class="mdescLeft">&#160;</td><td class="mdescRight">HighAddress is the physical MAX address of the subsystem address range.  <a href="#a185924b641edacf1f3b4ec5abda27345">More...</a><br/></td></tr>
<tr class="separator:a185924b641edacf1f3b4ec5abda27345"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae6bd625f0db55f41892d4fd53daf4fe1"><td class="memItemLeft" align="right" valign="top">XVidC_PixelsPerClock&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_tx_ss1___config.html#ae6bd625f0db55f41892d4fd53daf4fe1">Ppc</a></td></tr>
<tr class="memdesc:ae6bd625f0db55f41892d4fd53daf4fe1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Supported Pixel per Clock.  <a href="#ae6bd625f0db55f41892d4fd53daf4fe1">More...</a><br/></td></tr>
<tr class="separator:ae6bd625f0db55f41892d4fd53daf4fe1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9e46735ff88bd2caa3708090e66a9737"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_tx_ss1___config.html#a9e46735ff88bd2caa3708090e66a9737">MaxBitsPerPixel</a></td></tr>
<tr class="memdesc:a9e46735ff88bd2caa3708090e66a9737"><td class="mdescLeft">&#160;</td><td class="mdescRight">Maximum Supported Color Depth.  <a href="#a9e46735ff88bd2caa3708090e66a9737">More...</a><br/></td></tr>
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<tr class="memitem:a3d9c7f27b41ac6c3575679c8cff34227"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_tx_ss1___config.html#a3d9c7f27b41ac6c3575679c8cff34227">DynHdr</a></td></tr>
<tr class="memdesc:a3d9c7f27b41ac6c3575679c8cff34227"><td class="mdescLeft">&#160;</td><td class="mdescRight">&lt; Maximum FRL Rate Supporte  <a href="#a3d9c7f27b41ac6c3575679c8cff34227">More...</a><br/></td></tr>
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<tr class="memitem:a5c5d05779f4a6e3f55f868ef9e37994f"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_tx_ss1___config.html#a5c5d05779f4a6e3f55f868ef9e37994f">DSC</a></td></tr>
<tr class="memdesc:a5c5d05779f4a6e3f55f868ef9e37994f"><td class="mdescLeft">&#160;</td><td class="mdescRight">DSC Supported.  <a href="#a5c5d05779f4a6e3f55f868ef9e37994f">More...</a><br/></td></tr>
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<tr class="memitem:aa8205c90494b16611fb959bb27b10304"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_tx_ss1___config.html#aa8205c90494b16611fb959bb27b10304">AxiLiteClkFreq</a></td></tr>
<tr class="memdesc:aa8205c90494b16611fb959bb27b10304"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXI Lite Clock Frequency in Hz.  <a href="#aa8205c90494b16611fb959bb27b10304">More...</a><br/></td></tr>
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<tr class="memitem:a55587fe4cdd478faa025c97a26a3191f"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_tx_ss1___config.html#a55587fe4cdd478faa025c97a26a3191f">VideoInterface</a></td></tr>
<tr class="memdesc:a55587fe4cdd478faa025c97a26a3191f"><td class="mdescLeft">&#160;</td><td class="mdescRight">0 - AXI4S 1 - Native 2 - Native DE video interface  <a href="#a55587fe4cdd478faa025c97a26a3191f">More...</a><br/></td></tr>
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<tr class="memitem:ad7dff11e99b119ce7a8dd5286664bcd0"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_v___hdmi_tx_ss1___sub_core.html">XV_HdmiTxSs1_SubCore</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_tx_ss1___config.html#ad7dff11e99b119ce7a8dd5286664bcd0">HdcpTimer</a></td></tr>
<tr class="memdesc:ad7dff11e99b119ce7a8dd5286664bcd0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sub-core instance configuration.  <a href="#ad7dff11e99b119ce7a8dd5286664bcd0">More...</a><br/></td></tr>
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<tr class="memitem:ab0da29e56fdf9b2c32fc38b797f3ec88"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_v___hdmi_tx_ss1___sub_core.html">XV_HdmiTxSs1_SubCore</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_tx_ss1___config.html#ab0da29e56fdf9b2c32fc38b797f3ec88">Hdcp14</a></td></tr>
<tr class="memdesc:ab0da29e56fdf9b2c32fc38b797f3ec88"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sub-core instance configuration.  <a href="#ab0da29e56fdf9b2c32fc38b797f3ec88">More...</a><br/></td></tr>
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<tr class="memdesc:a24ce299ea4d8c6c7e1052ee2e83d4924"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sub-core instance configuration.  <a href="#a24ce299ea4d8c6c7e1052ee2e83d4924">More...</a><br/></td></tr>
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<tr class="memitem:a6c96b525bcc797ccaa4db3d8638bf09d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_v___hdmi_tx_ss1___sub_core.html">XV_HdmiTxSs1_SubCore</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_tx_ss1___config.html#a6c96b525bcc797ccaa4db3d8638bf09d">HdmiTx1</a></td></tr>
<tr class="memdesc:a6c96b525bcc797ccaa4db3d8638bf09d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sub-core instance configuration.  <a href="#a6c96b525bcc797ccaa4db3d8638bf09d">More...</a><br/></td></tr>
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<tr class="memitem:a551d6a6fa1e71515aead4eba79f11a46"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_v___hdmi_tx_ss1___sub_core.html">XV_HdmiTxSs1_SubCore</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_tx_ss1___config.html#a551d6a6fa1e71515aead4eba79f11a46">Vtc</a></td></tr>
<tr class="memdesc:a551d6a6fa1e71515aead4eba79f11a46"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sub-core instance configuration.  <a href="#a551d6a6fa1e71515aead4eba79f11a46">More...</a><br/></td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p>Video Processing Subsystem configuration structure. </p>
<p>Each subsystem device should have a configuration structure associated that defines the MAX supported sub-cores within subsystem </p>
</div><h2 class="groupheader">Field Documentation</h2>
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          <td class="memname">u32 XV_HdmiTxSs1_Config::AxiLiteClkFreq</td>
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<p>AXI Lite Clock Frequency in Hz. </p>

<p>Referenced by <a class="el" href="xv__hdmitxss1_8h.html#a33b732506d6578b5daf78406e2864af0">XV_HdmiTxSs1_CfgInitialize()</a>, and <a class="el" href="group__v__hdmitxss1.html#gac555201d618cc9e05b73a417f77701b2">XV_HdmiTxSs1_SubcoreInitHdmiTx1()</a>.</p>

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<p>BaseAddress is the physical base address of the subsystem address range. </p>

<p>Referenced by <a class="el" href="xv__hdmitxss1_8h.html#a33b732506d6578b5daf78406e2864af0">XV_HdmiTxSs1_CfgInitialize()</a>, <a class="el" href="xv__hdmitxss1_8h.html#aa8729d35447faa67579814df82d6955f">XV_HdmiTxSS1_SetHpdTolerance()</a>, <a class="el" href="group__v__hdmitxss1.html#gac555201d618cc9e05b73a417f77701b2">XV_HdmiTxSs1_SubcoreInitHdmiTx1()</a>, and <a class="el" href="group__v__hdmitxss1.html#ga64a794defc59694de323c4b239088906">XV_HdmiTxSs1_SubcoreInitVtc()</a>.</p>

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          <td class="memname">u16 XV_HdmiTxSs1_Config::DeviceId</td>
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<p>DeviceId is the unique ID of the device. </p>

<p>Referenced by <a class="el" href="xv__hdmitxss1_8h.html#a33b732506d6578b5daf78406e2864af0">XV_HdmiTxSs1_CfgInitialize()</a>.</p>

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          <td class="memname">u32 XV_HdmiTxSs1_Config::DSC</td>
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<p>DSC Supported. </p>

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<p>&lt; Maximum FRL Rate Supporte </p>
<p>Supports Dynamic HDR </p>

<p>Referenced by <a class="el" href="xv__hdmitxss1_8h.html#a175b839b0e0ec994f7e8771ce1c5753e">XV_HdmiTxSs1_DynHdr_Cfg()</a>, <a class="el" href="xv__hdmitxss1_8h.html#a7f6a8ade2c773f29e5b88e52838d6ba7">XV_HdmiTxSs1_DynHdr_Control()</a>, <a class="el" href="xv__hdmitxss1_8h.html#a49ba251f15947696114561c442cec65d">XV_HdmiTxSs1_DynHdr_DM_Control()</a>, <a class="el" href="xv__hdmitxss1_8h.html#a3ecc61ff3885370235c4af6beece925e">XV_HdmiTxSs1_DynHdr_GetErr()</a>, and <a class="el" href="xv__hdmitxss1_8h.html#ad98a7cc78ec71fed4cf3e53202f03863">XV_HdmiTxSs1_DynHdr_GOF_Control()</a>.</p>

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          <td class="memname"><a class="el" href="struct_x_v___hdmi_tx_ss1___sub_core.html">XV_HdmiTxSs1_SubCore</a> XV_HdmiTxSs1_Config::Hdcp14</td>
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<p>Sub-core instance configuration. </p>

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<p>Sub-core instance configuration. </p>

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<p>Sub-core instance configuration. </p>

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          <td class="memname"><a class="el" href="struct_x_v___hdmi_tx_ss1___sub_core.html">XV_HdmiTxSs1_SubCore</a> XV_HdmiTxSs1_Config::HdmiTx1</td>
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<p>Sub-core instance configuration. </p>

<p>Referenced by <a class="el" href="group__v__hdmitxss1.html#gac555201d618cc9e05b73a417f77701b2">XV_HdmiTxSs1_SubcoreInitHdmiTx1()</a>.</p>

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<p>HighAddress is the physical MAX address of the subsystem address range. </p>

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          <td class="memname">u8 XV_HdmiTxSs1_Config::MaxBitsPerPixel</td>
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<p>Maximum Supported Color Depth. </p>

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<p>Supported Pixel per Clock. </p>

<p>Referenced by <a class="el" href="xv__hdmitxss1_8h.html#a4026c5f96125675de1e423a0c1374923">XV_HdmiTxSs1_SetDefaultPpc()</a>, <a class="el" href="xv__hdmitxss1_8h.html#abc2436c5f1c1202e7fae694d62d74272">XV_HdmiTxSs1_SetPpc()</a>, and <a class="el" href="xv__hdmitxss1_8h.html#a706164018c12104b9b425ea36c7fb38f">XV_HdmiTxSs1_SetStream()</a>.</p>

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          <td class="memname">u8 XV_HdmiTxSs1_Config::VideoInterface</td>
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<p>0 - AXI4S 1 - Native 2 - Native DE video interface </p>

<p>Referenced by <a class="el" href="xv__hdmitxss1_8h.html#a706164018c12104b9b425ea36c7fb38f">XV_HdmiTxSs1_SetStream()</a>.</p>

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          <td class="memname"><a class="el" href="struct_x_v___hdmi_tx_ss1___sub_core.html">XV_HdmiTxSs1_SubCore</a> XV_HdmiTxSs1_Config::Vtc</td>
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<p>Sub-core instance configuration. </p>

<p>Referenced by <a class="el" href="xv__hdmitxss1_8h.html#a3f0a51a41b4b0a2f0a5f1d6df6adbf1e">XV_HdmiTxSs1_RegisterDebug()</a>, and <a class="el" href="group__v__hdmitxss1.html#ga64a794defc59694de323c4b239088906">XV_HdmiTxSs1_SubcoreInitVtc()</a>.</p>

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